1. Field of the Invention
The present invention relates to a semiconductor memory device used as a SRAM, DRAM, PROM, EPROM, EEPROM and the like and more particularly to a semiconductor memory device having redundancy memory cells provided in the direction of a column.
2. Description of the Related Art
Memory capacity of a semiconductor memory device tends to grow year by year. Accordingly, a chip area is increasing and, at the same time, a pattern is being scaled down further. As a result, it is becoming difficult to completely curb the occurrence of defective memory cells which cannot write or read data exactly or normally in one semiconductor memory device. To solve this, by mounting excessive memory cells (i.e., redundancy memory cells) that can provide additional memory capacity than required and by replacing defective memory cells with these redundancy memory cells, a yield of the semiconductor memory device is conventionally improved. When the number of bits used for inputting/outputting in one semiconductor memory cell was only 4 to 16, the use of the redundancy memory cells mounted in the direction of a row in the semiconductor memory device and adapted to replace defective memory cells with these redundancy memory cells on the same word line was mainstream to imporve the yield.
However, in recent years, the number of bits tends to increase and it has now become as large as 32 to 64. Additionally, some gate arrays and system-on-chips with the semiconductor memory device of this kind built-in are operated using the number of bits being 256 for inputting/outputting. Due to increased numbers of bits used for inputting/outputting in semiconductor memory cells, gate arrays or the like, fraction defective in memory cells disposed in the row direction, sense amplifiers, read/write buffers, etc., is becoming large. Accordingly, it is difficult to prevent the drop in the yield of semiconductor memory cells only by mounting the redundancy memory cell in the direction of the row.
To solve this problem, a semiconductor memory device having redundancy memory cells mounted in the direction of a column has recently been developed as disclosed, for example, in Japanese Laid-open Patent Application No. Hei 7-122096. FIG. 6 is a diagram showing a concept of electrical configurations of important features of a conventional semiconductor memory device disclosed in the above application. This semiconductor memory device, as shown in FIG. 6, is provided with "n" pieces of memory-cell columns 1.sub.1 to 1.sub.n, each having two or more memory cells. Of these memory-cell columns, the column 1.sub.n is a redundancy memory-cell column. Each of the memory-cell columns 1.sub.1 to 1.sub.n is connected to input-output nodes 2.sub.1 to 2.sub.n through each of corresponding bit lines. Between the input-output nodes 2.sub.1 to 2.sub.n adjacent to each other are placed "(n-1)" pieces of switches 3.sub.1 to 3.sub.n-1. A terminal Ta of each of these switches 3.sub.1 to 3.sub.n-1 is connected to a left side of each of input-output nodes 2 as shown in the drawing. A terminal Tb of each switch 3 is connected to a right side of each of input-output nodes 2.sub.1 to 2.sub.n as shown in the drawing and a terminal Tc of the switch 3 is connected to each of corresponding input-output lines 4.sub.1 to 4.sub.n-1. Though not shown, more than one word line is mounted in the direction of a row to connect each of memory-cell columns 1.sub.1 to 1.sub.n. When one of these word lines is activated, a desired memory cell is selected to allow reading and/or writing. Moreover, between the memory-cell columns 1.sub.1 to 1.sub.n and input-output nodes 2.sub.1 to 2.sub.n are mounted circuits, including a sense amplifier, column selecting circuit, read/write buffer and the like, required to make the memory cell read or write data.
FIG. 7 is a circuit diagram of a switch constituting the conventional semiconductor memory device. As depicted in FIG. 7, the switch 3 is composed of transfer NMOS transistors (hereinafter referred to as transistors) 11 and 12, transfer PMOS transistors (hereinafter referred to as transistors) 13 and 14 and an inverter 15. When a "high" level control voltage is applied to the terminal Td of the switch 3, the transfer NMOS 11 is turned on and the transfer PMOS 14 is turned off. At this point, since an output voltage of the inverter 15 goes "high", the transfer NMOS 12 is turned off and the transfer PMOS 13 is turned on. This causes the terminal Tc to be connected to the terminal Ta. On the other hand, when a "low" level control voltage is applied to the terminal Td of the switch 3, the transfer NMOS 11 is turned off and the transfer PMOS 14 is turned on. At this point, since an output voltage of the inverter 15 goes "high", the transfer NMOS 12 is turned on and the transfer PMOS 13 is turned off. This causes the terminal Tc to be connected to the terminal Tb. Then, the switch 3 is connected to the input-output line 4 corresponding to either of the input-output nodes 2 selected.
In FIG. 6, assuming that any one of memory cells constituting the memory-cell column 1.sub.4 is a defective memory cell (the memory-cell column containing defective memory cells is referred hereinafter to as a defective memory-cell column), a fuse 5.sub.4 is turned off and the terminal Tc of all switches 3.sub.1 to 3.sub.3 disposed on the left side of the memory-cell column 1.sub.4 is connected to the terminal Ta and the switching is made so that the switch can be connected to input-output nodes 2.sub.1 to 2.sub.3 disposed on the left side of these switches and, at the same time, the terminal Tc of all switches 3.sub.4 to 3.sub.n-1 disposed on the right side of the memory-cell column 1.sub.4 is connected to the terminal Tb and the switching is made so that the switch can be connected to input-output nodes 2.sub.4 to 2.sub.n-1 disposed on the right side of these switches.
Referring to FIG. 6, to set the switching direction of the switch 3, "n" pieces of fuses 5.sub.1 to 5.sub.n are connected in series. To one end of these fuses is applied a supply voltage Vcc and the other end of the same is connected to a position of ground GND through a resistor 6. Each point of connection between fuses 5 adjacent to each other is connected to the terminal Td of each of the switches 3 and a voltage at the point of connection is applied, as a control voltage, to each of the corresponding switches 3.
In the examination of the quality of the semiconductor memory device to see if it is defective or not, when any one (for example, fuse 5.sub.4 in FIG. 6) of the fuses 5 corresponding to the position of any defective memory-cell column (i.e., memory-cell column 1.sub.4 in FIG. 6) is shut off by a laser or the like, the voltage at a point of connection on the side of the power source Vcc with respect to any shut-off fuse 5 is set to go "high" and the voltage at a point of connection on the side of the position of the ground GND with respect to the shut-off fuse 5 is set to go "low", thus allowing the switching direction of the switch 3 to be set in a fixed manner.
In the above conventional semiconductor memory device, if, because the memory-cell column 1.sub.1 is the defective memory-cell column, the fuse 5.sub.1, not the fuse 5.sub.4, is shut off (see FIG. 6), all the control voltages go "low" and, in all switches 3.sub.1 to 3.sub.n-1, the transfer NMOS 12 and transfer PMOS 14 are turned on and, at the same time, the transfer NMOS 11 and transfer PMOS are turned off, causing the terminal Tc to be connected to the terminal Tb. In this case, the terminal Td of the switch 3 disposed near to the position of the ground GND (for example, switches 3.sub.n-1 or 3.sub.n-2) is easily held at a ground potential. However, the terminal Td of the switch 3 disposed far from the position of the ground GND (for example, the switch 3.sub.1) is hardly held at the ground potential and is driven in a state of easily picking up noises occurring in the surrounding atmosphere because of resistance and capacitance of fuses 5.sub.2 to 5.sub.n connected between the switch and the position of the ground GND and of the wiring installed to connect these fuses therewith.
In this state, if, for example, a level of a potential of data supplied to the input-output line 4.sub.1 is reversed from a "low" to a "high" for the data to be written in a memory-cell column 1.sub.2, a gate and drain of the transfer NMOS 11 are coupled respectively to a gate and drain of the transfer NMOS 12 owing to floating capacitance C.sub.NGD between the gates and the drains of the transfer NMOSs 11 and 12 (see FIG. 7), while a gate and source of the transfer PMOS 13 are coupled respectively to a gate and source of the transfer PMOS 14 owing to floating capacitance C.sub.PGS between the gates and the sources of the transfer PMOSs 13 and 14 (see FIG. 7) and, as a result, the gate voltage of each transistor may be changed instantaneously from a "low" to a "high" (this is called "coupling noise"). Because of this, there are some cases where the transfer NMOS 12 and transfer PMOS 14 become in the OFF state though it should be originally in the ON state, while the transfer NMOS 11 and transfer PMOS 13 become in the ON state though it should be originally in the OFF state. Then, if the terminal Ta of the switch 3.sub.1 is once connected to the terminal Ta, data is erroneously written in the defective memory-cell column 1.sub.1 to which data should not be originally written.
On the other hand, for example, if the fuse 5.sub.n, not the fuse 5.sub.4, is shut off because the memory-cell column 1.sub.n is defective and the memory-cell columns 1.sub.1 to 1.sub.n-1 is normal, all the control voltages go "high" and, as a result, in all the switches 3.sub.1 to 3.sub.n-1, the transfer NMOS 11 and transfer PMOS 13 are turned on and, at the same time, the transfer NMOS 12 and the transfer PMOS 14 are turned off, causing the terminal Tc to be connected to the terminal Ta. In this case, the terminal Td of the switch 3 disposed near to the power source Vcc (for example, switches 3.sub.1 or 3.sub.2) is easily held at the supply voltage Vcc. However, the terminal Td of the switch 3 disposed far from the power source (for example, the switch 3.sub.n-1) is hardly held at the supply voltage Vcc and is driven in a state of easily picking up noises occurring in the surrounding atmosphere because of the resistance and capacitance of fuses 5.sub.1 to 5.sub.n connected between the switch 3 and the power source and of the wiring installed to connect these fuses therewith. In this state, if, for example, a level of a potential of data supplied to the input-output line 4.sub.n-1 is reversed from a "low" to a "high" for the data to be written data in a memory-cell column 1.sub.n-1, a gate and drain of the transfer NMOS 11 are coupled respectively to a gate and drain of the transfer NMOS 12 owing to floating capacitance C.sub.NGD (see FIG. 7), while a gate and source of the transfer PMOS 13 are coupled respectively to a gate and source of the transfer PMOS 14 owing to floating capacitance C.sub.PGS and, as a result, the coupling noise occurs, causing the gate voltage of each of the transfer NMOSs and the transfer PMOSs to be changed instantaneously from a "low" to a "high" in some cases. Because of this, there are some cases where the transfer NMOS 12 and transfer PMOS 14 become in the ON state though it should be originally in the OFF state, while the transfer NMOS 11 and transfer PMOS 13 become in the OFF state though it should be originally in the ON state. Then, if the terminal Ta of the switch 3.sub.n-1 is once connected to the terminal Ta, data is erroneously written in the defective memory-cell column 1.sub.n to which data should not be originally written.
Due to malfunctions described above, data stored by this semiconductor memory device may be different from that originally stored, causing a malfunction of equipment employing this semiconductor memory device.
Similar malfunctions as described above may occur when data is read out. That is, when data read out from the memory cell is passed through the corresponding switch 3, if a level of a potential of the data is reversed from a "low" to a "high" or vice versa, due to floating capacitance C.sub.NGS between the gates and sources of the transfer NMOSs 11 and 12 and floating capacitance C.sub.PGD between the gates and drains of the transfer PMOSs 13 and 14 (see FIG. 7), the gate voltages of the transfer NMOSs 11 and 12 and the transfer PMOSs 13 and 14 are changed instantaneously from a "high" to a "low" or vice versa, thus causing the terminal Tc of the switch 3 to be connected to a terminal that should not be connected originally. As a result, the read-out data may contain values being shifted by one bit, causing malfunctions of equipment employing this semiconductor memory device. Moreover, if the malfunction described above had occurred at the time of writing data, the value of read data may be entirely different from that of data which should have been stored initially and the malfunction of the equipment using this semiconductor memory device is inevitable.